For the design of digital circuits on the scale of VLSI (very large scale integration) technology, designers often employ computer aided techniques. Standard languages such as Hardware Description Languages (HDLs) have been developed to describe digital circuits to aide in the design and simulation of complex digital circuits. Several hardware description languages, such as VHDL and Verilog, have evolved as industry standards. VHDL and Verilog are general purpose hardware description languages that allow definition of a hardware model at the gate level, the register transfer level (RTL) or the behavioral level using abstract data types. As device technology continues to advance, various product design tools have been developed to adapt HDLs for use with newer devices and design styles.
In designing an integrated circuit with an HDL code, the code is first written and then compiled by an HDL compiler. The HDL source code describes at some level the circuit elements, and the compiler produces an RTL netlist from this compilation. The RTL netlist can be a technology independent netlist in that it is independent of the technology or architecture of a specific vendor's integrated circuit, such as field programmable gate arrays (FPGA) or an application-specific integrated circuit (ASIC). The RTL netlist corresponds to a schematic representation of circuit elements (as opposed to a behavioral representation). A mapping operation is then performed to convert from the technology independent RTL netlist to a technology specific netlist which can be used to create circuits in the vendor's technology or architecture. It is well known that FPGA vendors utilize different technology or architecture to implement logic circuits within their integrated circuits. Thus, the technology independent RTL netlist is mapped to create a netlist which is specific to a particular vendor's technology or architecture.
A floor planning operation can then be applied to plan the layout of a particular integrated circuit and to control timing problems and to manage interconnections between regions of an integrated circuit. A typical floor planning operation divides the circuit area of an integrated circuit into regions, sometimes called “blocks,” and then assigns logic to reside in a block. After placement of components on the chip and routing of wires between components, timing analysis (e.g., timing simulation or static timing analysis) can be performed to accurately determine the signal delays between logic elements. Back annotation is typically performed to update a more-abstract design with information from later design stages.
A problem with very large scale integrated circuits is the propagation delay to different device locations, especially from the core to the peripheral of the integrated circuit. The following descriptions describe specifically the reset signal propagation delay, but the invention is not so restricted, and can be applied to reduce the propagation delay of other signals. The conventional prior art circuits typically treat reset signal as a global signal, meaning a reset source provides a reset signal to drive all the reset pins of the sequential elements. This approach can leave the sequential elements with an unpredictable state, especially after the termination of the reset signal for sequential elements located far away from the reset signal source. For example, consider two sequential elements with different propagation delays from the reset signal source. After the assertion of the reset signal, these sequential elements both get reset. Then the reset signal de-asserts just before the clock edge. The sequential element with a short propagation delay comes out of the reset state following the clock edge. The other element with a long propagation delay, however, may miss the clock edge, so it remains in reset state, damaging the circuit performance. This problem is more pronounced when sequential elements are distributed in remote areas of the circuit, such as in the peripheral areas for I/O (Input/Output) modules.